For instance, in an epitaxial silicon wafer to be used for a power MOS transistor, a silicon wafer of the epitaxial silicon wafer is required to have an extremely low substrate resistivity. In order to sufficiently decrease the substrate resistivity of the silicon wafer, there has been known a technique of doping arsenic (As) or antimony (Sb) as an n-type dopant for resistivity adjustment to molten silicon in a pulling step (i.e., at the time of growing a silicon crystal) of a single crystal ingot (hereinafter, referred to as a single crystal) as a material for a silicon wafer. However, since such a dopant is extremely volatile, it is difficult to sufficiently increase a dopant concentration in the silicon crystal, so that it is difficult to produce a silicon wafer having a resistivity as low as desired.
Accordingly, a silicon wafer having an extremely low substrate resistivity, which is doped with a highly concentrated phosphorus (P) as an n-type dopant having a volatility relatively lower than that of arsenic (As) or antimony (Sb), has been used.
On the other hand, since epitaxial growth occurs at a high temperature when producing an epitaxial silicon wafer, oxygen precipitates (BMD), oxygen precipitation nuclei or the like formed in the crystal during the growth of the single crystal are dissipated by the high temperature heat treatment, thereby lowering gettering ability.
In order to overcome the shortage in gettering ability, it is known to apply polysilicon back seal (PBS) before the epitaxial growing process. The polysilicon back seal is a kind of EG (External Gettering), in which a polysilicon film is formed on a backside of a silicon wafer to make use of strain fields or lattice mismatch created at an interface between the polysilicon film and the silicon wafer.
It was found that, however, when a polysilicon film is formed on a backside of a silicon wafer, a number of stacking faults (abbreviated as “SF” hereinafter) are generated on the epitaxial film, and the SF appearing on a top side of the silicon wafer in a form of steps significantly deteriorates LPD (Light Point Defect) level on the top side of the silicon wafer.
Accordingly, studies have been made in order to restrain the above disadvantage (see, for instance, Patent Literature 1).
Patent Literature 1 discloses that the generation of SF can be effectively restrained by forming a polysilicon film on a backside of a silicon wafer at a temperature of less than 600 degrees C.